1. Field of the Invention
This invention relates to a semiconductor memory device, specifically to a read only memory (hereafter referred to as a ROM).
2. Description of the Related Art
A mask ROM is a type of ROM, into which data is programmed during a manufacturing process using a photo mask. Programming methods include a diffusion layer programming, an ion implantation programming, a contact hole programming and so on. Generally speaking, the ion implantation programming can make the area per bit of the mask ROM smaller than shoes of the other programming methods. In particular, the area per bit of a mask ROM, which includes a plurality of memory transistors connected in series, is very small. Such a ROM is referred to as a stacked ROM hereinafter.
FIG. 4A and FIG. 4B are equivalent circuit diagrams of the stacked ROM. A group of memory transistors 10 includes four P-channel type memory transistors 1A, 1B, 1C and 1D connected in series. The group of memory transistors 10 is connected to a bit line BL. Gates of the memory transistors 1A, 1B, 1C and 1D are connected to word lines. The word lines are provided with outputs of a row decoder which is not shown in the figure.
The memory transistors 1A, 1B, 1C and 1D can be either an enhancement type or a depletion type depending on the selective ion implantation using a photo mask. Hereby each bit of data is programmed into each of the memory transistors 1A, 1B, 1C and 1D. In this example, it is assumed that the memory transistors 1B and 1D are depletion type while the memory transistors 1A and 1C are enhancement type. An enhancement type transistor has a normal threshold voltage. A depletion type transistor is always turned on regardless a voltage applied to its gate, since impurities of the same conductivity type as its source and drain are ion implanted into its channel.
In order to read the programmed data, first a pre-charge signal PC is set to high level so that an N-channel type MOS transistor 2 for pre-charge is turned on and a P-channel type MOS transistor 3 for readout power supply is turned off. At this time, all word lines are set to low level, thus all of the memory transistors 1A, 1B, 1C and 1D are turned on.
After that, the P-channel type MOS transistor 3 for readout power supply is turned on and the N-channel type MOS transistor 2 for pre-charge is turned off by turning the pre-charge signal PC low. Then a word line applied to a selected memory transistor is turned to high level while the other word lines are kept at low level. Herewith, reading of the data takes place.
When the memory transistor 1A is selected, the word line connected to its gate is turned to high level, as shown in FIG. 4A. The memory transistor 1A is turned off because it is enhancement type. Thus, a data readout line 6 connected to the pre-charge transistor 2 keeps low level (0V). And the stored data xe2x80x9c0xe2x80x9d of low level is latched with a latch circuit 19 through a sense amplifier 8. A voltage holding circuit 7 includes the sense amplifier 8 having an inverter and an N-channel type transistor 9 for keeping low level. The voltage holding circuit 7 is a circuit to hold the pre-charge level (0V) of the data readout line 6 stable. An output of the sense amplifier 8 is applied to a gate of the transistor 9 for keeping low level, while its drain is connected to the data readout line 6 and its source is grounded.
When the memory transistor 1B is selected, the word line connected to its gate is turned to high level, as shown in FIG. 4B. The memory transistor 1B is turned on because it is depletion type. The other memory transistors 1A, 1C and 1D are turned on because their gates are at low level. Therefore, a charging current I flows from the transistor 3 for readout power supply through the group of the memory transistors 10 and a column decoder 4, turning the data readout line 6 from low level to high level. And the stored data xe2x80x9c1xe2x80x9d of high level is latched with a latch circuit 19 through a sense amplifier 8.
However, the voltage holding circuit 7 causes a conflict over the level when the high level stored data xe2x80x9c1xe2x80x9d is read out from the memory transistor. That is, while the charging current I pushes the data readout line 6 to high level, a current flowing through the transistor 9 for keeping low level pulls the data readout line 6 to low level on the other hand, since the transistor 9 for keeping low level is turned on at the beginning of readout. For this reason, raising voltage of the data readout line 6 takes time, reducing reading rate for the high level stored data xe2x80x9c1xe2x80x9d. With this being the case, the transistor 9 for keeping low level has been designed to have high impedance in the conventional art.
When the impedance of the transistor 9 for keeping low level is high, however, there is a problem in reading a low level stored data xe2x80x9c0xe2x80x9d that the ability to keep low level is weakened, and the voltage holding circuit 7 is made vulnerable to a leakage current in a memory transistor, which flows into the data readout line 6 to change the low level to high level.
In addition, when the impedance of the transistor 9 for keeping low level is increased, the area of its gate is also increased, adding more oxide capacitance for the transistor 9 for keeping low level to charge. Therefore, when the high level stored data xe2x80x9c1xe2x80x9d is read out (while the transistor 9 for keeping low level is turned on), it takes longer time for the data readout line 6 to turn from low level to high level, thus making high rate readout impossible.
The invention provides a semiconductor memory device including a plurality of memory transistors connected in series, a data readout line to which data stored in the memory transistors is outputted, a pre-charging transistor pre-charging the data readout line to a first electric potential, and a sense amplifier connected to the data readout line. The device also includes a first holding transistor connected to the data readout line and controlled by an output of the sense amplifier, a second holding transistor connecting the first holding transistor and a voltage source at the first electric potential, and a delay circuit applying to the second holding transistor a signal for turning on the second holding transistor at a predetermined time after a start of a pre-charging of the data readout line by the pre-charging transistor.